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1 document # sram129 rev d revised july 2007 p4c1048l low power 512k x 8 cmos static ram locations are specified on address pins a 0 to a 18 . read- ing is accomplished by device selection ( ce low) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these condi- tions, the data in the addressed memory location is pre- sented on the data input/output pins. the input/output pins stay in the high z state when either ce is high or we is low. the p4c1048l is packaged in a 32-pin 445 mil plastic sop, 32-pin tsop ii, or 600 mil plastic or ceramic side- brazed dip. the p4c1048l is a 4 megabit low power cmos static ram organized as 512k x 8. the cmos memory re- quires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times as fast as 45 ns are availale. cmos is utilized to reduce power consumption to a low level. the p4c1048l device provides asynchronous opera- tion with matching access and cycle times. memory common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages ?32-pin 600 mil plastic and ceramic dip ?32-pin 445 mil sop ?32-pin tsop ii v cc current ? operating: 35ma ? cmos standby: 100a access times ?45/55/70/100 ns single 5 volts 10% power supply easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs description features functional block diagram pin configuration dip (p600, c10), sop (s12), tsop ii (t4) top view
p4c1048l page 2 of 12 document # sram129 rev d recommended operating temperature & supply voltage maximum ratings (a) stresses greater than those listed can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to maximum ratings for extended periods can adversely affect device reliability. temperature range (ambient) supply voltage 4.5v v cc 5.5v industrial (-40c to 85c) 4.5v v cc 5.5v commercial (0c to 70c) symbol parameter min max unit v cc supply voltage with respect to gnd -0.5 7.0 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 v cc + 0.5 v t a operating ambient temperature -55 125 c s tg -65 150 c i out output current into low outputs 25 ma i lat latch-up current >200 ma storage temperature military (-55c to 125c) 4.5v v cc 5.5v capacitances (d) (v cc = 5.0v, t a = 25c, f = 1.0 mhz) power dissipation characteristics vs. speed symbol parameter test conditions max unit c in c out input capacitance output capacitance v in = 0v v out = 0v 6 8 pf pf symbol parameter unit i cc dynamic operating current commercial industrial military 20 25 35 20 25 35 ma -70 -100 temperature range * * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e. ce and we v il (max), oe is high. switching inputs are 0v and 3v. notes: a. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. b. extended temperature operation guaranteed with 400 linear feet per minute of air flow. c. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. d. this parameter is sampled and not 100% tested. 20 25 35 20 25 35 -45 -55
p4c1048l page 3 of 12 document # sram129 rev d dc electrical characteristics (over recommended operating temperature & supply voltage) (b) i sb standby power supply current (ttl input levels) ce v ih mil. v cc = max, ind./com?l. f = max., outputs open ce v hc mil. v cc = max, ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 symbol v ih v il v hc v lc i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input leakage current test conditions v cc = max. mil. v in = gnd to v cc ind./com?l. v cc = max., mil. ce = v ih , ind./com?l. v out = gnd to v cc unit v v v v a a ma a v ol output low voltage (ttl load) i ol = +2.1 ma, v cc = min. v output high voltage (ttl load) v oh i oh = ?1 ma, v cc = min. v output leakage current p4c1048l ___ ___ 5 3 100 30 ___ ___ min 2.2 ?0.5 (c) v cc ?0.2 ?0.5 (c) ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 +10 +5 +10 +5 0.4 2.4 n/a = not applicable
p4c1048l page 4 of 12 document # sram129 rev d read cycle no. 1 ( oe oe oe oe oe controlled) (1) ac electrical characteristics - read cycle (over recommended operating temperature & supply voltage) symbol parameter -45 min max -100 min max unit t rc 45 ns t aa address access time 45 100 ns t ac chip enable access time 45 100 ns t oh output hold from address change 55 ns t lz chip enable to output in low z 10 10 ns t hz chip disable to output in high z 18 35 ns t oe output enable low to data valid 22 45 ns t olz output enable low to low z 55 ns t ohz output enable high to high z 18 35 ns t pu chip enable to power up time 00 ns t pd chip disable to power down time 45 100 ns read cycle time 100 55 55 20 25 20 55 70 70 25 35 25 70 55 5 10 5 0 70 5 10 5 0 -55 min max -70 min max
p4c1048l page 5 of 12 document # sram129 rev d notes: 1. we is high for read cycle. 2. ce and oe are low for read cycle. 3. address must be valid prior to, or coincident with later of ce transition low. read cycle no. 2 (address controlled) read cycle no. 3 ( ce ce ce ce ce controlled) 4. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 5. read cycle time is measured from the last valid address to the first transitioning address.
p4c1048l page 6 of 12 document # sram129 rev d -70 notes: 6. ce and we are low for write cycle. 7. oe is low for this write cycle to show t wz and t ow . 8. if ce goes high simultaneously with we high, the output remains in a high impedance state. 9. write cycle time is measured from the last valid address to the first transitioning address. ac characteristics - write cycle (over recommended operating temperature & supply voltage) write cycle no. 1 ( we we we we we controlled) (6,7) symbol parameter max -100 max unit min min t wc t cw t as t wp t ah t dh t wz t ow write cycle time 70 100 ns chip enable time to end of write 60 75 ns address valid to end of write 60 75 ns address set-up time 00 ns write pulse width 50 60 ns address hold time 00 ns data valid to end of write 35 45 ns data hold time 0 0 ns write enable to output in high z 25 35 ns output active from end of write 55 ns t aw t dw -55 max min 55 40 40 0 40 0 30 0 20 5 -45 max min 45 35 35 0 35 0 25 0 18 5
p4c1048l page 7 of 12 document # sram129 rev d write active read timing waveform of write cycle no.2 ( ce ce ce ce ce controlled) (6) * including scope and test fixture. note: because of the high speed of the p4c1048l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.77v (thevenin voltage) at the comparator input, and a 589 ? resistor must be used in series with d out to match 639 ? (thevenin resistance). ac test conditions truth table input pulse levels input rise and fall times input timing reference level output timing reference level output load gnd to 3.0v 3ns 1.5v 1.5v see fig. 1 and 2 mode standby d out disabled standby power i/o we we we we we oe oe oe oe oe ce ce ce ce ce high z d out d in x h h l x h l x h l l l active active high z figure 1. output load figure 2. thevenin equivalent
p4c1048l page 8 of 12 document # sram129 rev d data retention 1. ce 1 v dr -0.2v, ce 2 v dr -0.2v or ce 2 0.2v; or ce 1 0.2v, ce 2 - 0.2v; v in v dr -0.2v or v in 0.2v low v cc data retention waveform symbol parameter test conditions unit v dr i ccdr v cc for data retention data retention current ce v cc -0.2v, v in v cc -0.2v or v in 0.2v v v dr = 2.0v v dr = 3.0v a a t r operating recovery time chip deselect to data retention time see retention waveform ns ns t cdr max min 2.0 5.5 20 200 t rc 0 30 300 comm/ind military comm/ind military
p4c1048l page 9 of 12 document # sram129 rev d selection guide the p4c1048l is available in the following temperature, speed and package options. ordering information * military temperature range with mil-std-883 class b processing. 45 55 70 100 plastic dip (600 mil) -45pc -55pc -70pc -100pc side brazed dip (600 mil) -45cwc -55cwc -70cwc -100cwc plastic sop (445 mil) -45sc -55sc -70sc -100sc tsop ii -45tc -55tc -70tc -100tc plastic dip (600 mil) -45pi -55pi -70pi -100pi side brazed dip (600 mil) -45cwi -55cwi -70cwi -100cwi plastic sop (445 mil) -45si -55si -70si -100si tsop ii -45ti -55ti -70ti -100ti military side brazed dip (600 mil) n/a n/a -70cwm -100cwm military processed* side brazed dip (600 mil) n/a n/a -70cwmb -100cwmb industrial temperature range package speed (ns) commercial
p4c1048l page 10 of 12 document # sram129 rev d pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.680 e 0.510 0.620 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - 0.600 bsc 0.100 bsc c10 32 (600 mil) sidebrazed dual in-line package soic/sop small outline ic packages pkg # # pins symbol min max a-0.118 a1 0.004 - a2 0.101 0.111 b 0.014 0.020 c 0.006 0.012 d 0.793 0.817 e e 0.440 0.450 h 0.546 0.566 l 0.023 0.039 l1 0.047 0.063 0 4 s12 32 (445 mil) 0.050 bsc
p4c1048l page 11 of 12 document # sram129 rev d pkg # # pins symbol min max a 0.160 0.200 a1 0.015 - b 0.014 0.023 b2 0.045 0.070 c 0.006 0.014 d 1.600 1.700 e1 0.526 0.548 e 0.590 0.610 e eb l 0.120 0.150 0 15 p600 32 (600 mil) 0.100 bsc 0.600 bsc plastic dual in-line package pkg # # pins symbol min max a 0.037 0.041 a 2 -0.047 b 0.012 0.020 d 0.395 0.405 e 0.820 0.831 e h d 0.455 0.471 t4 32 0.050 bsc tsop ii package
p4c1048l page 12 of 12 document # sram129 rev d revisions document number : sram129 document title : p4c1048l low power 512k x 8 cmos static ram rev. issue date orig. of change description of change or oct-05 jdb new data sheet a nov-06 jdb minor corrections to dc electrical characteristics and data retention tables b dec-06 jdb update soic/sop package drawing. c may-07 jdb added 45/55 ns and pdip d jul-07 jdb corrected error in selection guide; added tsop ii package

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